Thank you for visiting the Zocalo Tech web site. We are in an exciting period for the company. The last two years have produced technology that allows us to introduce products that will help move SystemVerilog Assertion-Based Verification into the broader market. Over the next few months we will be creating the infrastructure for a Q1, 2009 introduction of our product set to the market. This includes a new website with on-demand demo capability.

In the meantime, here is an overview of the products to be introduced. Please do not hesitate to contact us at sales@zocalo-tech.com for any questions.

Zocalo Tech, Inc. Product Overview

Background

Zocalo's product focus is SystemVerilog Assertion-Based Verification (ABV). Assertion-Based Verification adds a whole new dimension to functional verification and is the emerging standard for complex functional verification. However, implementation has been slower than expected. A major bottleneck is that assertions are difficult to create and use. Once they are defined and coded they must be documented and instantiated in the design or testbench. To date verification engineers have been the primary users of assertions since they have no choice even with the difficulties.

Since the designer is intimately familiar with the design, adding assertions during the design stage can have significant impact on detecting problems early in the functional verification process. Many companies are pushing to have designer-provided assertions as part of the flow. However, the time required away from the design task is difficult to justify.

In an effort to make assertions easier to use, the industry standards organization Accellera created a free library of commonly-used assertions called the Open Verification Library or OVL. They are highly parameterized, allowing the user to provide many different assertions from one set of code. Each of the major EDA vendors has created an expanded version of OVL.

OVL and the EDA vendor libraries cover most of the needs of the designer. In spite of this, acceptance by designers has been limited because the task of instantiating the assertions in the design is tedious, error-prone, and time-consuming making the designer less than enthusiastic about using them.

For verification engineers, OVL is a net gain even though using them is "tedious, error-prone and time-consuming". However, they are too limited, requiring additional custom assertions. Custom assertions are referred as SVAs (SystemVerilog Assertions). They are time consuming to create and have limited reusability. Therefore in most cases new SVAs must be written from scratch. Writing them also requires verification and coding experience beyond the scope of the broader range of verification engineers.

Summary

• OVL covers most of the designer needs, however, ease of use issues have limited their acceptance.
• OVL is useful for verification engineers even though they are difficult to use. However, OVL is too limited for verification engineer requirements. Verification engineers must also provide custom assertions (SVAs).
• SVAs are difficult to code and have minimum reusability.

Zocalo software addresses the preceding with productivity software that fits into any SystemVerilog ABV flow.

Z-OVL

Z- OVL is a productivity tool addressing OVL ease of use. A summary of Z-OVL features accessed through an intuitive graphic user interface is as follows:

• Quickly select an appropriate OVL library component.
• Add the OVL component to a design element.
• Click-to-select valid values for most OVL parameters.
• Automatically create the design-specific documentation for a verification plan.
• Automatically create the file list of information required to run the simulator of choice.

Support of the three major EDA companies is accomplished by integrating company-specific capabilities.

• Support for company-specific assertion libraries that extend OVL.
• Cadence and Synopsys have verification plan software in their process. The automated verification plan documentation provided by Z-OVL is formatted for and exported to these programs, negating the necessity to enter it manually.
• Automatically create the file list required to run company-specific formal verification. Once the assertions are instantiated in the design, formal verification can take place. The ability to quickly move into formal verification and obtain immediate feedback is a major advantage.

Z-OVL will be provided in two versions:

• Z-OVL as described above, including the EDA company-specific libraries and interfaces.
• eZ-OVL is a low-cost tool with only OVL support and capable of instantiating OVL's to single design files. Designers and new users in many cases will prefer this approach.

Z-SVA

Z-SVA extends Z-OVL to include modification and extension of SVAs, and greater ease-of-use. This is made possible using technology unique to Zocalo:

• Zocalo's SystemVerilog parser provides incremental parsing and elaboration allowing on-the-fly updates to the code. This technology sets the stage for modifying and extending assertions within the verification environment.
• Zocalo has developed a specialized SystemVerilog code generator (patents pending). This allows Z-SVA to produce standard SystemVerilog code, while providing two powerful extensions to SystemVerilog:
  • Inheritance, allowing the creation of new assertions via extension or modification of existing code. This allows the benefits of object-oriented programming to be applied to complex assertions.
  • Template generation, providing the basis to create easily-reusable parameterized assertions.
• The SVAs and associated documentation lend themselves to creation of user/project/company libraries of assertions that can be modified or extended as required for reuse.