Zocalo Tech, Inc. is a privately funded Electronic Design Automation (EDA) company founded in 2005 developing technology to help verification engineers get the most from SystemVerilog functional verification.
SystemVerilog combines the latest technology in Hardware Description Language (HDL) and Hardware Verification Language (HVL) into a single software program for functional verification and design implementation. The starting point for the functional verification process is the verification plan. Since it is simply a written document, it immediately becomes obsolete as the design evolves and the verification team gains more insight into the design and what functionality must be verified. Attempts to keep the verification plan as the primary record for driving the overall process are marginal at best. This represents a major deficiency in the verification process.
"Verification plans today don't enable predictable, plan-driven verification. They are usually passive: an ad-hoc list of checklist items that are manually converted to tests. They cannot drive the day-to-day creation/execution of tests. Nor do they enable any automation for aggregating data from multiple sources, tracking the progress over time, and measurement against goals. The status of a project is left to the subjective judgment of individuals interpreting all the raw data. Automation of this entire process is a key requirement for more predictable verification."
Janick Bergeron, Synopsys Scientist and moderator, Verification Guild
2006 Design Automation Conference (DAC) verification panel
View minutes of discussion
Disconnect between the verification plan and the verification implementation has always been an issue. At previous levels of chip complexity, the problem was manageable. With the evolving use of SystemVerilog and the inherent increase in the level of complexity for System on a Chip (SoC) projects, fixing this deficiency is now a necessity.
Zocalo Tech's patent pending software, Ztest, will provide verification engineers with an effective approach to maintain the verification plan as the primary document driving the verification cycle.