Ztest
Ztest software provides the ability to create an intelligent verification plan that drives the SystemVerilog verification process.
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As modifications to any of the major parts of the verification process (verification plan, testbench or logic design) occur, the individual components are synchronized maintaining an up to date verification database.
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As tests are completed, the progress relative to each test is monitored and reported.
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The verification plan becomes a living document that provides the transition between the test requirements and implementation and serves as the communication vehicle between the Verification Engineers, Design Engineers and Management.
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Ztest simply enhances the existing methodology, it does not change it. The verification engineer still writes the verification plan and stimulus, works with the design engineers to assess the results and coverage and implements iterations to the verification plan. The difference is they are managing the process via Ztest in a structured, single source, intelligent environment.
For more information proceed to download
Ztest Product Description White Paper.
Zebra
Zocalo Tech is providing, Zebra, a freeware
Verilog/SystemVerilog design browser and Perl scripting environment. Zebra is the front end of Ztest. Zebra allows the user to access information from the SystemVerilog design and test bench. Zebra includes the Verilog parser/elaborator and Perl API.
In addition to the normal capabilities of a design browser, the user can easily interface to their own editor to see the source of the module or instantiation. A major value of Zebra is the ability to write Perl scripts to check/manipulate the design code.
If you think Zebra may be useful for your project, please contact sales@zocalo-tech.com for more information.
The software can be easily customized to suit your needs. If you are interested in purchasing a source code license, or in contracting a customization task to Zocalo Tech, please contact us at:
sales@zocalo-tech.com
- Supports source files in SystemVerilog, Verilog 2001, or Verilog
1995.
- One mouse click takes you to module or instance source in your
favorite editor.
- Perl API allows traversal of the design hierarchy.
- Iterate over the list of instances, or retrieve an
instance by name.
- View final parameter values, and whether the value was
set by a defparam or by the module instantiation.
- View the original source code location.
- View the preprocessed source of any module.
- Perl commands can be run in the interactive shell window,
or run from scripts.
Copyright (C) 2006-2007, Zocalo Tech, Inc.