Zazz v2.0

Zazz was developed with one goal in mind: reducing the cost of developing and utilizing System Verilog Assertions (SVA). Zazz addresses the two major costs associated with developing assertions:

Startup Cost
In order to start developing assertions you have to learn the System Verilog Assertions (SVA) language. The SVA language has a steep learning curve and it takes time to be proficient in the language. Zazz Visual SVA allows the newbie assertion developer to create complex temporal assertions without the need to understand complex SVA language syntax.

Debug Cost
Assertions must be debugged and verified that they are coded correctly. Poorly-coded assertions (or assertions that too loosely describe behavior) can actually increase verification time since these may cause false failures which must also be debugged.

Normally assertions cannot be debugged until a full design/verification environment has been created: both design and verification testbench has been coded and are relatively stable. In addition, with large design sizes, it is not uncommon to take up to 30 minutes to debug a single code change to an assertion.

Zazz Debug capability automatically creates a dedicated (independent of design or verification testbench) randomized testbench for each assertion or set of assertions. With Zazz Debug, the assertion developer can debug assertions without the need for the design and the verification testbench. It reduces the single code change debug time to seconds instead of minutes or hours.

Who are Zazz users?

Major semiconductor and System houses are using Zazz, along with IP developers.

Debug Assertions

Zazz Debug

The most basic feature of Zazz is the ability to simulate and debug assertions outside of the design/verification environment. It does this by creating a constrained randomized testbench around the assertion so that engineers can see the full range of behaviors allowed by the assertion rather than the limited range of behaviors that might be seen in an actual simulation. This is critical to creating effective assertions, since assertions that never fail (because they are too lax) or that fail inappropriately (because they do not properly describe intended behavior) are wasted effort and can actually slow the verification process.

Example of Zazz Debug

Using Zazz Debug is very simple. Here is an example:

  • In the Zazz Assertion Debug Window, write or cut/paste the assertion code.
  • Click on Start to generate 10 examples of passing stimulus for the assertion.
  • Zazz generates waveforms and opens the waveform viewer of your choice to display the assertion behavior.

How does Zazz Debug work?

While this functionality may seem like some form of formal verification, the resemblance is only on the surface. To be effective, formal verification requires a design as well as a reasonable set of assertions since the goal is to verify that the functionality of the block matches the requirements enforced by the assertions.

Zazz Debug, on the other hand, shows the full range of behavior allowed by an assertion. It does this without regard to the Verilog design to which the assertion may be bound. To generate the waveform, Zazz incorporates a powerful constraint solver that analyzes the assertion (or set of assertions) and generates a set of waveforms that exercise the assertion. The output from the constraint solver is then used to create a simple Verilog testbench to replay the vectors and allow the user to see the assertion’s behavior in the context of a simulation. Zazz supports the three major simulators (Synopsys VCS™, Cadence Incisive™, and Mentor Graphics Questa™) and their associated waveform viewers, as well as the Springsoft Verdi™ waveform viewer, to allow engineers to view and debug the assertion behavior just as they would a normal simulation.

Zazz Visual SVA

Zazz Visual SVA enables engineers come up the SVA learning curve by creating assertions graphically, removing the need to fully understand the complex SVA syntax. Even experienced engineers benefit from the ability to quickly create complex assertions that would have been extremely difficult to construct by hand.

Example of Using Zazz Visual SVA

Coming soon.

Back to Top