The functional verification process starts with a written verification plan defined by the chip designers and the verification engineers. The verification plan is a document which describes the tests to be accomplished and the expected outputs. The functional verification process consists of three components:

• Verification Plan: Written in text or spreadsheet form.
• Design: Written in Hardware Description Language (HDL)
• Testbench: Written in Hardware Verification Language (HVL)

As chip complexity has increased the functional verification software has been continuously upgraded to higher levels of abstraction in an effort to counter the complexity issues. The latest generation of software for functional verification is referred to as SystemVerilog. SystemVerilog combines the latest technology in HDL and HVL. The combined software runs in a significantly more efficient manner, with SystemVerilog becoming the standard methodology for complex chips.

What does Ztest do?

Zocalo's product, Ztest provides the capability to link the verification plan with the design logic and testbench. Today the verification plan is simply a written document that provides a starting point for functional verification but immediately becomes obsolete. Attempts to keep the verification plan in sync with the design logic and testbench implementation are marginal at best and represent a major deficiency in the verification process.

Using Ztest software in conjunction with SystemVerilog provides the following:

• As modifications to any of the major parts of the verification process (verification plan, testbench or design) occur, the individual components are synchronized maintaining an up to date verification database.
• As tests are completed, the progress relative to each test is monitored and reported.
• The verification plan becomes a living document, providing the transition between the test requirements and implementation, and serves as the communication vehicle between the Verification Engineers, Design Engineers and Management.

Ztest simply enhances the existing methodology... it does not change it. The verification engineer still writes the verification plan and testbench, works with the design engineers to assess the results and coverage and implements iterations to the verification plan. The difference is they are managing the process via Ztest in a structured, single source, intelligent environment.

How does Ztest help verification engineers get the most from SystemVerilog?

The adoption of SystemVerilog will bring many powerful features that can improve the verification process, but the learning curve will be steep for many of today's verification engineers. Verification engineers must be experienced in object oriented software design which is not prevalent within the traditional verification engineer skill set. Additionally, the SystemVerilog language represents a new generation of verification technology. With close to 600 pages of complex technical additions, it will take significant time for all but the most expert verification engineers to master.

Ztest impacts the SystemVerilog complexity issue by:

• Making it possible to leverage the talents of expert verification engineers among the broader base of verification engineers. The more experienced SystemVerilog verification engineer can address the difficult SystemVerilog tasks, such as creating complex testbenches, monitors and assertions while the rest of the verification team concentrates on the verification implementation and evaluation of the results.
• Providing the ability to create reusable libraries from the verification plan and verification implementation created in Ztest. Common tasks or components can be grouped together, and reused across design revisions or projects.

This powerful combination of leveraging expert SystemVerilog engineers and formalized Ztest reusability plays a major role in helping verification engineers get the most from SystemVerilog.

For further information proceed to Ztest Description White Paper.